1. Field of the Invention
The present invention relates to the field of electronic circuitry, and in particular to a level-shifting, or floating voltage source, circuit.
2. Description of the Related Art
In electronic equipment in general, and particularly for fast-moving segments such as portable consumer devices (e.g. mobile phones, MP3 players etc), there is a relentless push to use the latest processor technology to increase the device capability and feature set while reducing power and cost. As the next generation of processors becomes available, lower operating voltages are used than in previous-generation processors so as to allow a reduction in process feature size, i.e. W/L, that enables a greater level of integration. This is beneficial in terms of reduced die size, reduced die cost and reduced power consumption.
Such progress results in two design challenges for power supply circuitry (e.g. DC-DC converters) to service these processors: one induced by the choice of the value of the low voltage; the other by battery technology lagging behind the change to lower processor supply voltages.
(i) The reduction in processor supply voltage requires a much tighter control—in absolute terms—of the DC-DC converter output voltage under prevailing processor load and battery conditions. If the control over the processor supply voltage is not sufficient, problems with under- or overvoltage may occur; both are equally undesirable.(ii) Since the battery terminal voltage has not dropped appreciably, and the duty cycle of a DC-DC converter is given by the ratio of VOUT/VIN, duty cycles must therefore reduce. This, coupled with the desire for small external components, pushes the DC-DC converter to high operating frequencies, resulting in extremely short switch on i.e. conduction, times. The increase in switching speed afforded by the reduction in transistor feature size is not normally available for the power switches since the interface components must be rated to battery voltage.
Since small conduction periods i.e. on times, of the power switches are difficult to control, a more robust method needs to be found in order to control the lower processor output voltages with adequate accuracy. Fortunately, one such method exists: Valley Current Mode (VCM). This method of DC-DC loop control controls the input transistor off i.e. non-conduction, time, rather than the on time. For the low duty cycle required, the non-conduction time is longer than the conduction time, so is therefore easier to control. Also VCM DC-DC converters are known to offer an inherently higher bandwidth and an improved transient response
Consider a buck converter, with an inductor switched between a supply VIN and Ground by a PMOS transistor and an NMOS transistor respectively. Under high or medium current demand, the inductor current, composed of an average component and a ripple, remains above zero through every cycle. This is termed Continuous Conduction Mode (CCM). As the load current demand decreases, it is advantageous for efficiency reasons to alter the control so that the current in the inductor goes to zero for some of each cycle to avoid ripple being large enough to cause a reverse in the current in the inductor. This is termed Discontinuous Current Mode (DCM). At even lower load currents it is advantageous to “pulse-skip” so the PMOS switch does not recharge the inductor in some cycles, but this can lead to undesired behaviour.
These various modes present different control problems and dynamics, and it is important to be able to transition between modes seamlessly without transients appearing during change over. There is also the opportunity for other modes, where current is saved by using simpler control schemes adequate for lower currents, such as unclocked hysteretic modes. For low currents, it may even be advantageous to use a linear regulator such as an LDO (Low Drop Out) regulator rather than a switched voltage regulator. For optimum performance the open-loop transfer function has to be tightly toleranced, and internal signal swings maximized.
FIG. 1 shows a typical application where processor circuitry 101, which may, for example, be a processor of a portable electronic device, is supplied with a voltage VOUT (102) by a DC-DC converter 100. The DC-DC converter 100 receives an input voltage VIN (103) and an external clock signal CLK (104) and outputs the required voltage output VOUT (102). It is usual for the supply voltage of a processor to be reduced when the processor is idling in order to save power, and then to ramp up to a more normal operating voltage where the processor may achieve full operating speed. The processor circuitry 101 therefore provides voltage select signals VSEL (105) to the DC-DC converter 100 to select an appropriate voltage output VOUT. The voltage select signals may be digital signals for controlling a programmable element of the DC-DC converter, such as a level shifter, as will be described later. The DC-DC converter 100 may also be operable in various modes, as will be described later, and the processor circuitry may select a particular mode of operation by appropriate mode control signals MODE (106). It will be appreciated that DC-DC converters may be used to provide power to device sub-systems other than processors and the embodiments described herein are generally applicable to any DC-DC converter or switched voltage regulator used for any application.
A conventional current-mode buck (i.e. step down) DC-DC converter 200 is shown in simplified form in FIG. 2. The converter 200 comprises two nested feedback loops, an inner Current Control loop and an outer Voltage Control loop.
The Current Control loop block 201 takes an input signal VERROR and a current sense signal ISNS fed back from the output stage and generates pulse-width modulated drive signals for the output stage 202. The voltage on the output stage output node LX is switched between ground and supply, VIN, at a controlled duty cycle, resulting in a triangular current waveform in the inductor L. The inductor L and output capacitor C1 act as a filter to reduce voltage ripple on the average voltage VOUT at an output node 203.
In operation the inductor current is sensed, and compared with VERROR. So this feedback loop generates an output sensed current varying according to the input signal VERROR. In many conventional DC-DC converters the sensed current is a peak current, although it is known to use an average current in some converters. In embodiments of the present invention to be described the minimum or “valley” current is used to control the duty cycle of the converter.
Variation of the delivered output current, smoothed by the output filter L, C1, modulates the output voltage at VOUT. This voltage VOUT is fed back, translated down to an appropriate voltage VOUT—LS by a Level Shifter, or Voltage Shifter, block 204, to the input of a Voltage Error Amplifier block 205. The Voltage Error Amplifier block 205 compares this processed version of VOUT with a supplied reference voltage VREF and provides the error signal VERROR signal which drives the above described inner feedback loop to close the outer feedback loop and thus stabilize VOUT at the desired voltage.
The Level Shifter 204 is illustrated as a resistive potential divider. The level shifter applies a conversion to the level of VOUT such that, when VOUT is equal to the desired or target output voltage, the level shifted signal VOUT—LS has a known relationship to the reference voltage VREF (e.g. the level shifted signal VOUT—LS may be equal to VREF when VOUT is exactly the desired output voltage). The Level Shifter 204 may be programmable, mechanically or digitally, to provide different voltage scaling or shifting circuitry, so as to allow the converter to be configurable to output different values of VOUT. For instance, it may be programmable by a digital multi-bit signal, such as the VSEL signal generated by a processor as shown in FIG. 1.
The Voltage Error Amplifier 205 is illustrated as an Operational Transconductance Amplifier (OTA) 206 driving an RC network 207, but could be some other amplifier. Generally it may include some passive impedances to provide closed-loop stabilization.
The Current Loop Control block 201 receives a signal 208 from the output stage 202 which passes through a Current Sensor Amp block 209 to pre-condition it, for instance to scale or strobe the signal, representative of the inductor current, to generate a convenient current sense signal ISNS. A duty modulator 210 compares the ISNS signal to the input VERROR to derive drive signals of the appropriate duty cycle to drive the output stage devices (10, 20) on and off via a Switch Driver buffer stage 211. The Duty Modulator 210 may require a clock signal 212 and a Ramp Generator 213 to generate the necessary sequence of pulses as would be understood by one skilled in the art. The Ramp Generator 213 may generate a slope compensation ramp signal which may be added either in whole or in part to the ISNS signal and/or the VERROR signal so as to prevent sub-harmonic oscillations as would be well understood by one skilled in the art.
The Output Stage 202 in general will have a high-side driver device such as a PMOS transistor 10 to switch the output to the high-side supply rail 214 (VIN) and a low-side driver device such as an NMOS transistor 20 to switch the output to the low-side supply rail 215 (Ground). The Stage 202 is also required to supply information, i.e. an indication, of inductor current signal 208, to feed back to the Current Control block 201.
The DC-DC converter 200 of FIG. 2 requires a voltage shifter, e.g. a potential divider, to translate the output voltage VOUT down to a (nominally) convenient reference voltage. Also this is a convenient place to adjust or trim the converter output voltage VOUT by use of a programmable voltage shifter.
FIG. 3 shows one way of creating a variable output voltage for the DC-DC converter 200. A programmable level shifter block 204 is shown, connected to an OTA block 206, such as described previously with respect to FIG. 2.
The programmable level shifter block 204 comprises a first resistor 301 and a second resistor 302 connected in series in a resistive potential divider arrangement. The level-shifted voltage VOUT—LS is taken from a node in between the two resistors 301, 302. The level-shifted voltage VOUT—LS is provided to an inverting input of the OTA block 206, with a VREF block 303 providing a reference voltage VREF to the non-inverting input.
In operation, the OTA 206 and the other components of the feedback loops will adjust VOUT until VOUT—LS becomes equal to VREF. Then VOUT=VREF·+ΔV where ΔV=VREF where β=R301/R302. The output voltage of the DC-DC converter 200 may thus be programmed by arranging the first resistor 301 in block 204 as a programmable resistance, programmed using the VSEL digital bus. The output voltage may also be programmed by making the second resistor 302 in block 204 an element with programmable conductance.
However, both of these programming solutions suffer from a common problem in that as the voltage codes are changed (i.e. the programmable resistance or conductance is altered), the gain from VOUT to VOUT—LS provided by the level-shifter block 204 changes as 1/(1+β). Since this gain is a factor in the overall open-loop gain response, this results in extra variation in the voltage error loop gain-bandwidth or unity gain frequency, especially in cases where a large variation in voltage is required. The extra design margin to achieve adequate closed-loop gain accuracy and stability, for example, despite this extra tolerance, impacts the performance typically exhibited (for instance the transient recovery response time and overshoot). A more subtle problem with the programmable conductance approach is that it uses large resistor values which may consume large areas of silicon real estate.